This invention relates generally to an analog circuit and technique, and more specifically to an analog offset cancellation technique and to a circuit and amplifier using that technique.
As the semiconductor industry advances, the size of individual devices used in the fabrication of integrated circuits continues to shrink. The shrinking of device sizes has many advantages, including the ability to implement more and more complex circuit functions on a single semiconductor device. But the shrinking of device sizes also has its drawbacks. One of the most serious drawbacks encountered with submicron device sizes results from transistor mismatches as is explained below. Often a circuit design requires the matching of two or more transistors or other devices. If those devices do not match precisely, an undesired offset in some circuit parameter may result. That offset, in turn, may result in some unwanted circuit behavior, or may even cause the circuit to fail completely. Small mismatches in devices can result from differences in insulator thicknesses, differences in device or element size or spacing, variations in the crystalline structure of the semiconductor material, and the like. These small mismatches become more significant as the device size shrinks. A small mismatch may be tolerable with large devices, but a mismatch of the same magnitude may be intolerable with small devices, because the mismatch represent a greater percentage of the overall device characteristic as the total device size shrinks.
The effect of device mismatch is especially apparent on the overall behavior of analog blocks such as operational amplifiers or Gm-C filters. The effects of device mismatch can result in the generation of unwanted offset voltages. The resulting offset, in turn, is most troublesome in analog transceiver chains that contain several amplifying blocks. In such a chain a small input analog signal is detected and may undergo several stages of amplification. Amplifying the useful signal also amplifies all parasitic signals that accompany that detected useful signal. Among the parasitic signals may be an offset voltage caused by the mismatch of transistors in the chain. A small offset voltage, after several stages of amplification, can result in a significant and undesirable parasitic voltage added to and perhaps even masking the desired signal.
There are several ways to reduce offset voltage in an analog circuit, but most are sampled solutions. This means that a switching scheme is used to reduce the offset voltage by memorizing the offset voltage on a capacitor during a first time slot and thereafter subtracting it from the signal during a later time slot. Such solutions are complex, require many devices, and consume considerable power. A need therefore existed for an analog offset cancellation technique that provides a continuous way of reducing the offset and which can be easily derived from existing circuits and circuit techniques.